This invention relates to a full adder for processing N-bit binary numbers, and particularly relates to a full adder the input and output of which are both performed optically.
FIG. 7 shows an example of a prior art parallel full adder, which is composed of a half adder, a plurality of full adders and a serial-parallel converter circuit. Shown by numeral 71 is a half adder in the first stage, 72 is a full adder, and 73 is a serial-parallel converter circuit. Symbols A and B represent input signals, S.sub.0, S.sub.1 and S.sub.2 are output signals, and C.sub.0, C.sub.1 and C.sub.2 are CARRY signals.
FIG. 8 shows an example of a prior art series full adder, which is composed of a full adder 81 and a latch memory 82. Symbols A and B represent input signals, S.sub.0, S.sub.1 and S.sub.2 are output signals, C is a CARRY signal, and R is a reset signal for the latch memory 82.
For performing the function of full addition of N-bit numbers, the parallel type circuit shown in FIG. 7 requires (N-1) full adders 72 and one half adder 71, so the resulting full adder circuit increases in size, requiring complicated wiring. Further, parallel processing of data in separate bits necessitates the use of the circuit 73 for achieving serial to parallel conversion of the input data.
Compared to the parallel full adder circuit of FIG. 7, the series type circuit shown in FIG. 8 has the advantage of simplicity in circuit configuration. On the other hand, the need for repeatedly performing the function of full addition by N times in succession results in very slow computing speed in the case where the full adder is composed of an ordinary electronic circuit.